Layout for NAND flash memory array having reduced word line impedance - Micron Technology, Inc.

Layout for NAND flash memory array having reduced word line impedance - Micron Technology, Inc.

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日期:2025-05-11
Layout for NAND flash memory array having reduced word line impedance United States Patent 7248499 Abstract: A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which ...看更多