Verilog - Keywords - verilog.renerta.com

Verilog - Keywords - verilog.renerta.com

瀏覽:804
日期:2025-04-24
always and assign begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endcase endfunction endmodule endprimitive endspecify endtable endtask event for force forever fork function highz0 highz1 if initial inout inp...看更多