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日期:2024-09-19
The NCP51199 is a linear regulator designed to supply a regulated VTT termination voltage for DDR-2 and DDR-3 memory applications.The regulator is capable of ... The NCP51199 is a linear regulator designed to supply a regulated VTT termination voltage for...
Sink/Source DDR Termination Regulator - Analog, Embedded Processing, Semiconductor Company, Texas In
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日期:2024-09-16
TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPS51200DRCR VSON DRC 10 3000 330.0 ......
TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, D
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日期:2024-09-18
1 2 7 9 3 5 4 6 VTT VTTSNS PGND VTTREF VDDQSNS VLDOIN S3 S5 TPS51206 10 VDD GND 8 PowerPad VTT VTTREF UDG-11024 S3_SLP S5_SLP 5 V or 3.3 V Supply VDDQ Product Folder Sample & Buy Technical Documents Tools & Software Support &...
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日期:2024-09-13
Features DDR Power Supply, Termination and Reference High Efficiency: Up to 94% Dual Outputs with ±3A Output Current Capability 2.25V to 5.5V Input Voltage Range ±1% Output Voltage Accuracy V TT Output Voltage Down to 0.5V Shutdown Current ≤1μA ......
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日期:2024-09-15
The SSTL_2 specification requires adequate output current drive so that parallel termination schemes can be used. The use of parallel termination is important for high-speed signaling, since it allows proper termination of the bus transmission lines, whic...
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日期:2024-09-12
VTT and VREF Considerations for DDRx SDRAM Devices The termination voltage (VTT) supply must sink and source current at one-half output voltage (1/2 VDDQ). This means that a standard switching power supply cannot be used without a shunt to allow for the ....
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日期:2024-09-17
Hardware and Layout Design Considerations for DDR Memory Interfaces, Rev. 6 6 Freescale Semiconductor Layout Order for the DDR Signal Groups Each ground or power reference must be solid and continuous from the BGA ball through the end termination....
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日期:2024-09-12
Feature/Option DDR DDR2 DDR2 Advantage Package 66-pin TSOP 54-, 60-ball FBGA 60-, 84-ball FBGA 63-ball FBGA DDP Enables better electrical performance and speed, dual die package enables higher densities Voltage (core and I/O) Low volt 2.5V-2.6V N/A...