search:ddr termination相關網頁資料

- zh.wikipedia.org
  
  DDR3 SDRAM - 維基百科，自由的百科全書
  
  第三代雙倍資料率同步動態隨機存取記憶體（Double-Data-Rate Three Synchronous Dynamic Random Access Memory，一般稱為DDR3 SDRAM），是一種電腦記憶體規格。它屬於 SDRAM 家族的記憶體產品，提供了相較於 DDR2 SDRAM 更高的執行效能與更低的電壓，是DDR2 SDRAM（四倍資料率 ...
  
  2024-05-01
  
  瀏覽：814
- knightkasim.pixnet.net
  
  DDR vs DDR2 vs DDR3特性比較 @ kasim的部落格 :: 痞客邦 PIXNET ::
  
  DDR, DDR2與DDR3的記憶體介面缺口都在不同位置，因此，彼此是不相容的，必須配合主機板上的插槽購買相對應的DDR型號。 DDR SDRAM 模塊用於桌上型電腦，被稱為 ...
  
  2024-05-04
  
  瀏覽：1465

ddr termination的相關文章

ddr termination的相關公司資訊

ddr termination的相關商品

NCP51199: DDR Termination Regulator, 2 A - Semiconductor and Integrated Circuit Devices

日期：2024-05-03

The NCP51199 is a linear regulator designed to supply a regulated VTT termination voltage for DDR-2 and DDR-3 memory applications.The regulator is capable of ... The NCP51199 is a linear regulator designed to supply a regulated VTT termination voltage for...

全文

Sink/Source DDR Termination Regulator - Analog, Embedded Processing, Semiconductor Company, Texas In

日期：2024-05-05

TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPS51200DRCR VSON DRC 10 3000 330.0 ......

全文

TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, D

日期：2024-05-01

1 2 7 9 3 5 4 6 VTT VTTSNS PGND VTTREF VDDQSNS VLDOIN S3 S5 TPS51206 10 VDD GND 8 PowerPad VTT VTTREF UDG-11024 S3_SLP S5_SLP 5 V or 3.3 V Supply VDDQ Product Folder Sample & Buy Technical Documents Tools & Software Support &...

全文

LTC3618 - Dual 4MHz, ±3A Synchronous Buck Converter for DDR Termination - Linear Technology

日期：2024-05-08

Features DDR Power Supply, Termination and Reference High Efficiency: Up to 94% Dual Outputs with ±3A Output Current Capability 2.25V to 5.5V Input Voltage Range ±1% Output Voltage Accuracy V TT Output Voltage Down to 0.5V Shutdown Current ≤1μA ......

全文

DDR SDRAM Signaling Design Notes

日期：2024-05-05

The SSTL_2 specification requires adequate output current drive so that parallel termination schemes can be used. The use of parallel termination is important for high-speed signaling, since it allows proper termination of the bus transmission lines, whic...

全文

DDR Memories Comparison and Overview|Freescale

日期：2024-05-05

VTT and VREF Considerations for DDRx SDRAM Devices The termination voltage (VTT) supply must sink and source current at one-half output voltage (1/2 VDDQ). This means that a standard switching power supply cannot be used without a shunt to allow for the ....

全文

Hardware and Layout Design Considerations for DDR Memory Interfaces

日期：2024-05-03

Hardware and Layout Design Considerations for DDR Memory Interfaces, Rev. 6 6 Freescale Semiconductor Layout Order for the DDR Signal Groups Each ground or power reference must be solid and continuous from the BGA ball through the end termination....

全文

DDR to DDR2 - Micron Technology, Inc.

日期：2024-05-06

Feature/Option DDR DDR2 DDR2 Advantage Package 66-pin TSOP 54-, 60-ball FBGA 60-, 84-ball FBGA 63-ball FBGA DDP Enables better electrical performance and speed, dual die package enables higher densities Voltage (core and I/O) Low volt 2.5V-2.6V N/A...

全文

12 > »