Nityanand's Weblog

Nityanand's Weblog

瀏覽:947
日期:2024-05-20
** Note: We have used common term parameters applicable for verilog designs. In VHDL the ‘Generics’ are used for the same. We use different parameters/generics in the verilog/vhdl designs. Parameters give us huge re-usability of the codes. It means we can...看更多